1. Field of the Invention
The present invention relates to semiconductor devices used as interface between individual systems and particularly to semiconductor devices having a 3-state output function.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing input and output portions of a conventional semiconductor device having a 3-state output function, using a complementary metal-oxide semiconductor (CMOS) circuit.
Construction thereof will be described with reference to FIG. 1. An inverter 1 constituting the input portion comprises a P channel metal-oxide semiconductor (MOS) transistor Q1 and an N channel MOS transistor Q2 connected in series between a power supply terminal 2 as a first power supply for application of a power voltage Vcc of high potential and a ground terminal 3 as a second power supply. A node N2 as a common connection point of the gates of the two MOS transistors Q1 and Q2 is connected to a data input terminal 5 through an input protection resistance 4. Input protection diodes 6 and 7 for surge absorption are connected between a node N1 as a connection point of the data input terminal 5 and the protection resistance 4 and the power supply terminal 2, and between the node N1 and the ground terminal 3, respectively.
On the other hand, a P channel MOS transistor Q3 and and N channel MOS transistor Q4 constituting the output portion are connected in series between the power supply terminal 2 and the ground terminal 3, and a connection point of the MOS transistors Q3 and Q4 is used as an output terminal 8. An internal circuit 9 is provided between the input portion and the output portion. The internal circuit 9 has inputs connected to a node N3 of the transistors Q1 and Q2, a node N4 of an output enable terminal 10, the power supply terminal 2 and the transistor Q3, and a node N5 of the ground terminal 3 and the transistor Q4, respectively, while it has outputs connected to the respective gates of the transistors Q3 and Q4. Thus, the internal circuit 9 controls the MOS transistors Q3 and Q4 of the output portion based on an output signal of the inverter 1 and a signal applied to the output enable terminal 10. Concrete examples of construction of the internal circuit 9 are shown in FIGS. 2 and 3.
Referring to FIG. 2, P channel MOS transistors Qc1, Qc2 and Qc3 and an N channel MOS transistor Qc4 are connected in series between a terminal 2a connected to the node N4 shown in FIG. 1 and a terminal 3a connected to the node N5 shown in FIG. 1. A P channel MOS transistor Qc5 and N channel MOS transistors Qc6, Qc7 and Qc8 are connected in series between a terminal 2b connected to the node N4 and a terminal 3b connected to the node N5. A P channel MOS transistor Qc9 and an N channel MOS transistor Qc10 are connected in series between a terminal 2c connected to the node N4 and a terminal 3c connected to the node N5. The node N3 is connected to the respective gates of the transistors Qc1, Qc2, Qc6 and Qc8, and the output enable terminal 10 is connected to the respective gates of the transistors Qc3, Qc4, Qc9 and Qc10. A connection point of the transistors Qc1 and Qc2 and a connection point of the transistors Qc5 and Qc6 are connected to constitute an output connected to the transistor Q3. A connection point of the transistors Qc3 and Qc4 and a connection point of the transistors Qc7 and Qc8 are connected to constitute the other output connected to the transistor Q4. A connection point of the transistors Qc2 and Qc3 and a connection point of the transistors Qc6 and Qc7 are connected. The gate of the transistor Qc5 and a connection point of the transistors Qc9 and Qc10 are connected to the gate of the transistor Qc7.
Operation of the internal circuit thus constructed will be briefly described. Let us assume an example in which a signal of high level (referred to hereinafter as H level) is applied as an output of the node N3, that is, the inverter 1, and an enable signal [a signal of low level (referred to hereinafter as L level)] is applied from the output enable terminal 10. The transistor Qc8 is turned on and the output to be supplied to the transistor Q4 changes to L level through conduction in the terminal 3b connected to the ground terminal. L level of the enable signal changes to H level through the transistors Qc9 and Qc10 of the inverter. As a result, the transistor Qc7 is turned on, while the transistor Qc5 is turned off. Since the transistor Qc6 is turned on upon receipt of the H level signal of the node N3, the transistors Qc6, Qc7 and Qc8 are all turned on and the output to be supplied to the transistor Q3 is transmitted through the terminal 3b and falls to L level.
When the L level signal is applied to the node N3 and the enable signal falls to L level, the outputs to be supplied to the transistors Q3 and Q4 all become the H level signals. On the other hand, when the enable signal rises to H level, the output signal to be supplied to the transistor Q3 rises to H level and the output signal to be supplied to the transistor Q4 falls to L level irrespective of the signal level at the node N3.
Referring to FIG. 3, construction of the internal circuit is the same as in FIG. 2, except that the transistors Qc2 and Qc6 in FIG. 2 are not provided. Relations among the signal at the node N3, the enable signal and the output signals are entirely the same as in FIG. 2.
Needless to say, constructions different from the above described constructions of the internal circuit may be also applied to the semiconductor device shown in FIG. 1 insofar as output signals are controlled as described above.
The input and output portions of the conventional semiconductor device having the 3-state output function are constructed as described above. If a signal of a predetermined level (L level) is applied to the output enable terminal 10 to bring the output portion into an enabled state, a signal dependent on the signal applied to the data input terminal 5 is obtained at the output terminal 8. For example, if the signal of L level is applied to the data input terminal 5, the output of H level is obtained from the inverter 1 and it is received by the internal circuit 9, so that a gate voltage of L level is applied therefrom to the MOS transistors Q3 and Q4 of the output portion. As a result, the MOS transistor Q3 is turned on and the MOS transistor Q4 is turned off, whereby the signal of H level is outputted at the output terminal 8. On the other hand, if the signal of H level is applied to the data input terminal 5, the output of the inverter 1 is of L level and upon receipt of the output, the internal circuit 9 applies a gate voltage of H level to the MOS transistors Q3 and Q4 of the output portion. As a result, the MOS transistor Q3 is turned off and the MOS transistor Q4 is turned on, whereby the signal of L level is outputted at the output terminal 8.
On the other hand, when the signal level applied to the output enable terminal 10 is changed to H level, the output portion is brought into a disabled state. More specifically, the gate voltage of H level is applied from the internal circuit 9 to the MOS transistor Q3 and the gate voltage of L level is applied from the internal circuit 9 to the MOS transistor Q4 as described above. As a result, the MOS transistors Q3 and Q4 are both turned off and the output terminal 8 is brought into a high-impedance state.
As described above, three kinds of output states appear at the output terminal 8 and those states are controlled according to operation timing in systems connected thereto.
The conventional semiconductor device having the 3-state output function uses the P channel MOS transistor Q3 and the N channel MOS transistor Q4 in the output portion as described above.
FIG. 4 is a schematic sectional view showing the output portion. As shown, P type impurity regions 32 and 33 to be drain and source regions of the transistor Q3 are formed on a major surface of an N.sup.- type semiconductor substrate 30, the impurity region 32 to be the source region being connected with the power supply terminal 2. The power supply terminal 2 is also connected with an N type impurity region 31 formed on the major surface of the semiconductor substrate 30 to apply the power supply voltage to the substrate. Further, a P.sup.- type well 34 is formed on the major surface of the semiconductor substrate 30 and N type impurity regions 35 and 36 to be drain and source regions of the transistor Q4 and a P type impurity region 37 to be a grounding contact of the well 34 are formed on the major surface of the well 34. The ground terminal 3 is connected to the impurity regions 36 and 37 and the output terminal 8 is connected to the impurity regions 33 and 35. In the above described structure, parasitic diodes 11 and 12 are formed between the output terminal 8 and the power supply terminal 2 and between the output terminal 8 and the ground terminal 3, respectively.
FIG. 5 is a circuit diagram in which the output portion of FIG. 1 is connected to another system.
As shown, the output terminal 8 of the semiconductor device having the 3-state output function is connected with an output terminal 15 of the system 14 having a power supply terminal 13 to which another power supply voltage Vcc' is supplied. In this case, when the supply of power to the semiconductor device having the 3-state output function is stopped to keep the device in the high-impedance state and only the system 14 is operated. Then, the output terminal 15 of the system 14 attains H level and electric current flows to the power supply terminal 2 through the parasitic diode 11. As a result, the power supply terminal 2 rises to H level to bring about a state as if the power supply voltage stopped were applied to the power supply terminal 2. In consequence, this voltage might be applied to the internal circuit 9, causing the transistor Q4 to be turned on or erroneous operation to occur making it difficult to keep the high-impedance state of the device.
FIG. 6 is a circuit diagram in which the input portion of FIG. 1 is connected with another system.
Referring to FIG. 6, the data input terminal 5 of the semiconductor device having the 3-state output function is connected with an output terminal 18 of the system 17 having a power supply terminal 16 to which another power supply voltage Vcc" is supplied. In this case, when the supply of power to the semiconductor device having the 3-state output function is stopped and only the system 17 is operated, the output terminal 18 of the system 17 attains H level and electric current flows to the power supply terminal 2 through the input protection diode 6. As a result, the level of the power supply terminal 2 is raised to H level and erroneous operation might occur in the semiconductor device having the 3-state output function. Although this problem will be solved on the input side if the input protection diode 6 is removed, such solution involves another disadvantage that input electrostatic dielectric strength is considerably lowered.
A gate protection circuit using an input clamp diode is disclosed in page 469 of QMOS DATA BOOK BY RCA SOLID STATE. However, this document does not suggest any formation of a semiconductor device having high electrostatic dielectric strength without a path to a high-potential power supply as provided according to the present invention and it does not disclose any idea of such device either.